The present invention relates to a phase-locked loop (PLL) circuit and, more particularly, to a PLL with a phase lock detection circuit.
Phase-locked loops (PLLs) are found in a myriad of electronic applications such as communication receivers and clock synchronization circuits for computer systems. A conventional PLL includes a phase detector for monitoring the phase difference between an input signal and an output signal of a voltage controlled oscillator (VCO) and generating an up control signal and a down control signal for a charge pump circuit which charges and discharges the loop filter at the input of the VCO. The up and down control signals drive the VCO to maintain a predetermined phase relationship between the signals applied to a phase detector, as is well understood.
It is common for the PLL to lose phase lock should the input signal fade or jump to a radically different frequency of operation. The out-of-lock state can be detected with a detection circuit and the system processing suspended until the PLL can re-achieve phase lock. Most, if not all, such lock detection schemes monitor the up control signal and the down control signal at the output of the phase detector to ascertain the lock status of the PLL. If the up control signal and down control signal are not pulsing, then loop node voltage remains substantially constant and the PLL should be in phase lock. When the up control signal and the down control signal are steadily generating pulses charging or discharging the loop filter to adjust the input voltage of the VCO, the loop must be in motion and thus out of phase lock.
During normal operation, the loop node is continuously subjected to leakage through the charge pump circuit thus requiring occasional pulses to maintain the voltage controlling the VCO. However, these intermittent pulses should not indicate an out-of-lock state. The conventional detection circuit typically includes a delay circuit comprising, for example, a string of serially coupled inverters designed to ignore short intermittent pulses from the phase detector having less than a predetermined pulse width. The up and down control signals must have a pulse width as least as long as the delay circuit to trigger an out-of-lock signal. Unfortunately, the pulse widths of the up and down control signals are subject to temperature and process variation and therefore are not well suited as control parameters for ascertaining phase lock. The pulse widths of the up and down control signals are merely rough indicators having limited accuracy of the true phase relationship between the input signals of the phase detector.
Hence, what is needed is an improved detection circuit for a PLL which directly monitors the input signals of the phase detector to determine the lock status of the loop.
It is therefore an object of the present invention to provide a phase lock detection circuit for a PLL circuit in order to supply stable phase lock information.
To attain the above and other objects, according to an aspect of the present invention there is provided a phase lock detection circuit including: a capacitor; a first constant current source for supplying a first constant current; a second constant current source for supplying a second constant current corresponding to M-times (M is an integer of two and more) the first constant current; a window signal generating circuit responsive to the output signal, for generating a window signal which has a pulse width corresponding to an acceptable phase error; a delay circuit for delaying the input signal; a detection circuit for detecting whether the delayed input signal is within the pulse width of the window signal or not and generating a detection signal as a detection result; a first circuit for supplying the first constant current as a charging source of the capacitor or providing a discharge path thereto in response to both a control signal and the detection signal during a first state when the input and output signals are not phase locked; a second circuit for supplying the second constant current as a charging source of the capacitor or providing the discharge path thereto in response to both the control and detection signals during a second state when the input and output signals are phase locked; and a first inverter coupled to the capacitor, for outputting the control signal in accordance with a voltage level developed across the capacitor, wherein during the first state, a charging time of the capacitor is longer than a discharging time thereof, and during the second state, the charging time of the capacitor is more short than the discharging time thereof.
The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.